Target Audience: This course is designed for technically experienced professionals involved in PCIe-based FPGA system design, including: Verification and validation engineers developing PCIe compliance and stress test strategies, System architects evaluating PCIe topology, bandwidth, and FPGA suitability for a new design, Hardware engineers responsible for PCIe endpoint design, transceiver bring-up, and hardware debug, FPGA designers implementing PCIe IP, clocking structures, resets, and Avalon interconnects inside the FPGA fabric, and Embedded software / driver engineers writing PCIe enumeration, BAR-mapped register access, interrupt service routines, and DMA drivers.

Course Description

This advanced course teaches experienced FPGA designers how to architect, implement, bring up, and validate PCIe links using Altera® FPGAs—from initial lane-up through reliable high-throughput data movement. The emphasis is not on “click-through IP setup,” but on understanding why PCIe link training succeeds or fails, how to build a robust endpoint architecture around Altera’s PCIe IP, and how to debug real-world issues spanning transceivers, resets/clocks, LTSSM behavior, configuration space, BAR mapping, interrupts, DMA, and system software interaction.

Participants learn a repeatable methodology for: selecting a workable PCIe architecture (Gen/lanes/clocking/topology); integrating Altera PCIe IP into a scalable FPGA design; building a clean control/data plane (register map, interrupts, streaming data path); and validating the interface under stress while maintaining timing closure and long-term maintainability.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is intended for engineers and architects who need to design, integrate, or verify 10 Gigabit Ethernet interfaces in Altera FPGA based systems. Specifically, the course is well-suited for: System Architects responsible for defining the datapath architecture and IP selection strategy for high-bandwidth FPGA platforms, Hardware Engineers designing PCBs, managing signal integrity, and working with high-speed serial interfaces, FPGA / RTL Design Engineers implementing and integrating Altera IP into production RTL designs using Quartus Prime Pro, Verification Engineers developing testbenches and simulation environments for 10GbE MAC and PHY IP, Software / Embedded Engineers developing drivers or control plane software that interacts with an FPGA hosted 10GbE subsystem, and Test and Validation Engineers responsible for functional and performance verification of 10GbE interfaces on production hardware.

Course Description

This course focuses on how to use Altera® IP solutions to build a 10 Gigabit Ethernet design targeting Altera® transceiver devices using the Quartus® Prime Pro software. You will learn how the Low Latency 10Gb Ethernet MAC IP is a flexible solution and how it provides many ways to customize and control its behavior for your application. You will also learn the features of the transceiver and the PHY IP, how to configure and connect the IP for your application, how to generate design examples to accelerate your understanding and implementation, and how to configure the MAC IP and incorporate it into your design as a 1G/2.5G/5G/10G Ethernet application.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is designed for technical professionals working on high-bandwidth networking products based on Altera Agilex 9 FPGAs. The primary audience includes: System Architects responsible for partitioning networking functions between FPGA fabric, embedded processors, and external ASICs; defining interface standards and performance budgets, Hardware Engineers designing PCBs and high-speed serial interfaces (QSFP28, QSFP-DD, CAUI-4), signal integrity analysis, transceivers, and power delivery for 100G/400G line-card designs, FPGA/RTL Design Engineers implementing Ethernet MAC, PCS, RS-FEC, and datapath logic in Altera Quartus Prime using Agilex 9 hard IP blocks and custom fabric, Embedded Software / Firmware Engineers developing device drivers, QSFP module management firmware (CMIS 4.x/SFF-8636), PTP clock servo algorithms, and platform management interfaces, and Verification & Test Engineers developing simulation testbenches, BFMs, and hardware test plans for 100GbE/400GbE subsystems.

Course Description

This course provides engineers and architects with an in-depth understanding of high bandwidth Ethernet networking at 100GbE and 400GbE using Altera’s Agilex 9 FPGA platform. Participants will progress from foundational Ethernet concepts beyond 10GbE through to the design, implementation, verification, and optimization of production-ready networking subsystems.

The course addresses the complete signal chain: physical coding sublayers, forward error correction (RS-FEC), multilane aggregation (CAUI-4, CAUI-16), PCS/MAC architecture, QSFP28/QSFP-DD module management, precision timing with PTP/IEEE 1588, and system level integration using Altera’s High Speed Ethernet (HSE) IP and Platform Designer. Lab sessions reinforce every major concept with hands-on exercises.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: This course is designed for engineers who design, architect, or validate high speed serial interfaces on Altera SoC based platforms. Typical participants include: System Architects responsible for selecting transceiver-based connectivity solutions and defining interface partitioning between FPGA fabric, hard IP, and external components, Hardware/PCB Engineers who design the board-level signal path, manage power delivery and decoupling for SerDes supplies, and verify physical layer compliance, FPGA Design Engineers who instantiate and configure Altera transceiver IP, write RTL for custom PCS logic, and integrate protocol stacks into the FPGA fabric, Verification and Validation Engineers responsible for transceiver bring-up, compliance testing, margin characterization, and regression of high-speed links, and Software/Embedded Engineers developing device drivers, link training firmware, or diagnostic software for systems that include high-speed serial peripherals (PCIe, Ethernet, etc.).

Course Description

This course teaches engineers how to design, bring up, validate, and debug high speed serial links using Altera® SoC devices. Participants acquire the knowledge and hands-on experience necessary to create stable, standards compliant, and fully verified high speed links from first principles through production-ready implementation. The curriculum blends rigorous transceiver architecture theory — covering PMA/PCS layer internals, clocking topologies, reset sequencing, and calibration flows — with practical Quartus® Prime tool workflows including the Transceiver Toolkit, the Link Planner, and on-chip debug infrastructure. Real world techniques such as adaptive equalization, jitter budgeting, link training protocols, IBIS-AMI simulation methodology, and board-level signal integrity practices are woven throughout every module.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is designed for System architects, hardware (RTL/SoC) engineers, and embedded/system software engineers building or evaluating CXL-attached FPGA platforms.

Course Description

The course treats CXL as a system problem spanning three audiences. System architects get the protocol model, coherency semantics, topology, and the tradeoffs that decide where CXL helps. Hardware engineers get the Altera hard-IP integration path, Platform Designer subsystem construction, and verification. Software engineers get the Linux CXL subsystem, memory tiering, device drivers, and the management/telemetry surface. Each day pairs lecture modules with a guided lab so all three audiences leave able to specify, build, and validate a CXL attached FPGA design.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: This course is designed for experienced engineers and architects working on embedded SoC designs who need to implement or evaluate multi-processor software architectures. The primary target audience includes: System Architects designing multi-processor SoC subsystems, evaluating AMP vs. SMP partitioning strategies, and specifying inter-processor communication architectures, Hardware Engineers responsible for FPGA/HPS interface design, memory mapped peripherals, shared memory regions, interrupt routing between processors, and hardware platforms, Embedded Software Engineers developing firmware, RTOS applications, Linux BSP customization, device drivers, and inter-processor communication middleware using OpenAMP and RPMsg, Verification and Integration Engineers validating multi-processor SoC designs and qualifying AMP software stacks for production, and FPGA Design Engineers who interface their RTL designs with the HPS subsystem and need to understand the software implications of their hardware decisions.

Course Description

This course provides comprehensive, hands-on training in Asymmetric Multi-Processing (AMP) design using Altera platforms. Participants will master the OpenAMP framework, RPMsg inter-processor communication, Linux and Zephyr RTOS co-execution, shared memory management, and production-grade boot sequencing for multi-core SoC products.

The course begins with single-core HPS programming and Linux BSP fundamentals, then progressively addresses AMP designs where one core runs Linux and another runs a bare-metal or RTOS workload. A dedicated module covers Heterogeneous SoC multi-processor design including both AMP and SMP configurations using the OpenAMP framework.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: This course is designed for System & hardware architects selecting memory technology and budgeting bandwidth, latency, power, and reliability, FPGA design engineers integrating EMIF/HBM IP, building data paths, and closing timing, Embedded & firmware engineers bringing up HPS-attached memory and managing shared buffers and coherency, Hardware/PCB engineers implementing DDR/LPDDR/HBM channels with the required signal-integrity discipline, Verification engineers building BFM/UVM environments for the memory subsystem, and Test & validation engineers characterizing margin, running soak tests, and qualifying boards for production.

Course Description

This course builds complete mastery of external memory interfaces on Altera FPGAs and SoCs — from DRAM protocol internals through board design, IP integration, system architecture, bring-up, debug, and production qualification. It includes dedicated coverage of ECC/RAS, signal integrity simulation, memory subsystem verification, power and thermal estimation, legacy and soft controller bring-up, registered memory (RDIMM/LRDIMM) and SPD, memory security, and cache coherency.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: This course is designed for professionals who develop or assess FPGA-based systems in safety critical domains, including automotive, industrial automation, medical devices, and aerospace. The primary target roles are: System Architects responsible for overall safety architecture and safety concept definition for systems containing FPGAs, Hardware Engineers designing FPGA logic, PCB integration, or mixed signal interfaces for safety-critical applications, Embedded Software Engineers developing firmware or drivers that interact with safety relevant FPGA IP blocks, Verification & Validation Engineers creating test plans, fault injection frameworks, and safety analysis artifacts, and Functional Safety Managers / Assessors overseeing the safety lifecycle and conducting internal or third-party assessments.

Course Description

Safety critical systems increasingly incorporate FPGAs, requiring designers to follow rigorous functional safety standards such as IEC 61508, ISO 26262, and IEC 62061. This course provides a comprehensive, hands-on treatment of the principles, processes, and Altera FPGA device features needed to develop FPGA-based designs that can be certified to the appropriate safety integrity level.

Participants will learn how to apply safety architecture patterns—such as redundancy, voting logic, and safe state design—to real FPGA projects. The course examines both systematic failure mitigation (development process discipline) and random hardware failure mitigation (diagnostic coverage, probabilistic failure metrics). Altera safety capable device families are studied in depth, including their built-in self test (BIST) resources, error detection/correction (EDAC) mechanisms, and lockstep processing support.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: This course is designed for professionals involved in SoC system design, implementation, and verification, including: FPGA design engineers with hands-on Altera tool experience seeking deeper system-level expertise, System architects responsible for SoC partitioning and hardware/software co-design, Hardware engineers designing RTL for FPGA fabric, custom IP, and AXI bus infrastructure, Embedded software engineers developing device drivers, BSPs, and Linux kernel modules for SoC targets, and Verification engineers building UVM testbenches and applying formal methods to SoC designs.

Course Description

This advanced course brings together all disciplines of Altera® SoC FPGA design into a comprehensive system design and verification experience. Students tackle the full SoC design cycle — system partitioning, hardware architecture, FPGA RTL implementation, Linux BSP, software integration, and system-level verification.

Participants work with the Altera Agilex™ and Cyclone® V SoC platforms to explore hard processor system (HPS) architecture, AXI interconnect design, custom IP integration, and high-performance DMA data paths. The course leverages UVM-based verification methodology and advanced formal verification techniques alongside physical hardware bring-up and software integration.

Course Duration: 3 Days

Course Level: Level 3

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