Target Audience: This course is designed for: System Architects defining signal processing architectures and evaluating algorithm trade-offs before committing to hardware, Hardware Engineers who need a structured DSP foundation before progressing to FPGA implementation courses, Software Engineers implementing or integrating DSP algorithms in embedded or real-time systems, DSP / Algorithm Engineers prototyping new algorithms and analyzing their performance in software, Verification Engineers building Python-based testbenches and analysis frameworks for DSP IP, and Engineers returning to DSP who want a structured, Python-first refresher course.

Course Description

This course provides a rigorous, unified foundation in Digital Signal Processing (DSP) theory while simultaneously building a professional Python-based prototyping and analysis workflow. It delivers a tightly sequenced progression from first principles to production-ready Python tooling. Beginning with the mathematics of discrete-time signals, the course progresses through frequency-domain analysis, filter design, multirate systems, and adaptive filtering. Every theoretical concept is immediately expressed and validated in Python using NumPy, SciPy, and Matplotlib, giving participants a practical toolkit they can apply the day they return from training.

Course Duration: 3 Days

Course Level: Level 2

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Target Audience: This course is designed for: Engineers who have completed the “DSP Fundamentals using Python Prototyping” course and are ready to move from Python prototyping to FPGA hardware, Hardware / RTL Engineers with FPGA experience who want to implement production DSP subsystems using HDL and Altera IP cores, System Architects evaluating FPGA-based DSP solutions who need to understand implementation cost, throughput, and latency tradeoffs, Software Engineers porting DSP algorithms to FPGA who need to develop HDL implementation skills, Verification Engineers building simulation environments and testbenches for DSP IP cores.

Course Description

This course teaches engineers how to design, implement, verify, and optimize high-performance DSP systems on Altera FPGA devices using both hand-coded RTL HDL and Altera’s production-grade IP cores. It is the second course in the FPGA Authority Progressive DSP Training Program and assumes that participants have completed the “DSP Fundamentals & Python Prototyping” course or possess equivalent DSP theory knowledge.

All DSP theory — sampling, filter design, FFT mathematics, adaptive filtering — is assumed as prior knowledge. The course opens at the RTL level and focuses entirely on hardware implementation concerns: how to map DSP algorithms to Altera DSP blocks and memory resources, how to write synthesis-efficient HDL pipelines, how to configure Altera IP cores, and how to close timing on multi-clock DSP systems.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is designed for: Software Engineers working on FPGA-based processing platforms who need to understand the hardware generation flow for integration and debug purposes, DSP / Algorithm Engineers who develop algorithms in MATLAB/Simulink and need to translate them into production-quality FPGA hardware using a model-based flow, Hardware / RTL Engineers who want to adopt a model-based design methodology to accelerate development and improve verification confidence, System Architects designing high-performance signal processing subsystems who need to evaluate architectural tradeoffs early in the design cycle, and Verification Engineers responsible for functional and hardware-accurate sign-off of DSP subsystems.

Course Description

This advanced course teaches experienced FPGA and DSP engineers how to use Altera DSP Builder in a model-based design workflow to create, optimize, verify, and deploy high-performance signal processing systems on Altera FPGAs. It is the third course in the FPGA Authority Progressive DSP Training Program.

The course assumes complete familiarity with DSP fundamentals and Altera FPGA architecture. The emphasis is entirely on the DSP Builder methodology: translating algorithm intent captured in MATLAB/Simulink into production-quality FPGA hardware through controlled HDL generation, hardware-accurate verification, and system-level integration.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is designed for: Research Engineers applying machine learning to signal processing and needing to evaluate FPGA deployment options, Senior DSP Engineers who are ready to apply their skills to complete application-domain systems, Systems Engineers designing radar, communications, or SDR products who need to bridge algorithm-level DSP and FPGA implementation, Algorithm Engineers developing communications receivers, pulse-compression radar, or spectrum sensing systems, FPGA Architects responsible for the top-level signal processing architecture of multi-domain products.

Course Description

This advanced course is the fourth in the FPGA Authority Progressive DSP Training Program. It covers application domain DSP topics that go beyond the general purpose building blocks taught in the prerequisite DSP courses from FPGA Authority: communications DSP, radar and sonar signal processing, software-defined radio, and machine learning assisted signal analysis.

The course is structured around complete system case studies rather than isolated building blocks. Each day explores a real world application domain from system-level architecture and performance budgeting skills applicable to communications, radar, and SDR, concluding with machine learning for signal classification.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: This course is designed for: Verification Engineers building testbenches and analysis tools for image processing IP cores, Hardware / FPGA Engineers designing real-time image processing or video pipeline systems on Altera FPGAs, Algorithm Engineers developing computer vision or image analysis algorithms who need to map them to FPGA hardware, System Architects designing embedded vision systems, machine vision cameras, or video surveillance products, Software Engineers working on image processing subsystems who need to understand hardware pipeline constraints, and DSP Engineers with 1D signal processing backgrounds who are moving into the 2D image/video domain.

Course Description

This course extends the FPGA Authority Progressive DSP Training Program into the domain of image processing and video. It applies and deepens the signal processing foundations — sampling, filtering, transforms, and fixed-point arithmetic — in the context of two-dimensional signals, real-time video pipelines, and image analysis algorithms.

Beginning with the theory of 2D signals and 2D transforms, the course progresses through spatial filtering, frequency-domain image processing, image compression, video pipeline architecture, and advanced topics including deep learning for visual inference on FPGA. Every concept is developed first in Python using NumPy, SciPy, and OpenCV, and then implemented in hardware-efficient FPGA architectures using RTL HDL, Altera IP cores, and Platform Designer.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: FPGA and hardware engineers with no prior ML/AI background who are transitioning into AI acceleration roles, Embedded software engineers responsible for deploying inference workloads on edge platforms, RTL designers and verification engineers who need to understand the AI workloads they are implementing or validating, System architects evaluating FPGA-based AI solutions who require ML model-level understanding, Recent graduates entering the FPGA AI field.

Course Description

This foundational course provides hardware engineers, FPGA designers, and embedded software engineers with the machine learning and deep learning knowledge required to participate effectively in AI hardware acceleration projects. Starting from first principles of supervised learning and progressing through convolutional neural networks, Transformer architectures, quantization mathematics, and the end-to-end model development and deployment lifecycle, participants build the vocabulary and intuition needed to engage in hardware-focused AI work. The presentation material is complimented with hands-on lab exercises. Concepts are reinforced through examples —  parameter counts, FLOP budgets, memory bandwidth demands, and precision tradeoffs — so that participants leave ready to engage directly with Altera AI Suite and HLS-based accelerator development.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: ML engineers and data scientists who need to understand the FPGA substrate to collaborate effectively with hardware engineers, FPGA engineers new to AI workloads who need to map ML concepts to fabric resources, System architects evaluating Altera FPGA solutions for edge AI applications, and Verification engineers requiring architectural understanding of inference accelerator designs.

Course Description

This course develops systematic and detailed understanding of the Altera FPGA device family and the Quartus Prime Pro ecosystem as applied to AI inference acceleration. Participants progress from FPGA fabric primitives (ALMs, DSP blocks, M20K SRAM, HBM2e) through the Agilex AI Tensor block architecture, memory subsystem design, AXI4 interfaces, and structured performance benchmarking methodology. The course bridges the conceptual gap between ML model characteristics and FPGA hardware resources, providing the architectural vocabulary and toolchain fluency. Extensive use of Quartus Prime Pro, Platform Designer, Signal Tap, and the Agilex 5 development kit ensures participants leave with practical device-level competency.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: FPGA engineers responsible for integrating deep learning IP into Quartus Prime Pro designs and meeting timing and resource constraints, Software and embedded engineers developing host side inference applications using the AI Suite runtime API, Machine learning engineers and data scientists who need to optimize and deploy trained models on Agilex FPGA targets, System architects evaluating FPGA-based inference solutions who need end-to-end toolchain familiarity, and Engineers who have completed the FPGA Authority “FPGA Architecture and AI Acceleration Survey” course and are ready to work with the full AI Suite toolchain.

Course Description

This course provides comprehensive, hands-on expertise with the Altera FPGA AI Suite — the end-to-end toolchain for generating AI accelerators targeting specific latency, throughput, and power requirements on Agilex FPGA devices. Custom models using the OpenVINO Model Optimizer and custom extension framework is also explored.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: Hardware engineers responsible for custom RTL or HLS accelerator IP development for AI inference on Altera FPGAs, FPGA engineers who need to implement inference kernels below the AI Suite abstraction level, Research and development engineers exploring novel network architectures or custom operators not supported by the AI Suite, Verification engineers who need to understand accelerator internals to develop effective validation strategies, and Engineers targeting maximum performance/watt for specialized inference applications through custom kernel design.

Course Description

This advanced course develops the skills to design, optimize, and integrate custom AI inference accelerator kernels using Altera HLS Compiler Pro, the Altera FPGA SDK for OpenCL, and RTL/SystemVerilog on Altera FPGAs. Participants work at the lowest level of the acceleration stack: implementing Conv2D, GEMM, depthwise separable convolution, multi-head attention, and activation function kernels from scratch; applying advanced HLS optimization techniques (pipelining, unrolling, dataflow, memory partitioning); designing systolic array architectures; implementing Transformer and attention mechanisms in hardware; and integrating all components into complete Platform Designer systems through AXI4 and AXI4-Stream interfaces.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: System architects and senior FPGA engineers targeting safety-critical applications: automotive ADAS, medical imaging, industrial automation, avionics, Safety engineers responsible for producing ISO 26262 or IEC 61508 compliance evidence for FPGA-based AI components, Security engineers responsible for threat modelling, secure boot, and key management for deployed edge AI systems, Technical leads who must make architectural decisions that balance safety, security, performance, and cost, and Certification engineers and tool qualification specialists working on FPGA AI product certification.

Course Description

This specialization course equips senior FPGA engineers, system architects, and safety engineers with the knowledge and practical skills to design, certify, and secure AI inference systems on Altera FPGA platforms. Covering the ISO 26262, IEC 61508, and IEC 62304 functional safety standards in depth, hardware safety mechanisms (TMR, SEU scrubbing, EDAC, watchdog timers), FPGA security architecture (AES bitstream encryption, ECDSA authentication, ARM TrustZone with OP-TEE), and AI model safety (adversarial robustness, OOD detection, runtime monitoring), the course translates regulatory and standards requirements into concrete hardware and software design decisions. Extensive labs provide hands-on experience with Altera safety IP, SEU injection, secure boot configuration, and OP-TEE Trusted Application development.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: Senior FPGA AI engineers and technical leads responsible for taking products from development through production operation, DevOps and MLOps engineers adapting their practices to FPGA AI firmware and model artifacts, System architects designing the production infrastructure for fleets of edge AI FPGA devices, Product managers and engineering managers who need to understand the operational complexity and cost of FPGA AI fleet deployment, and Engineers who are ready to address production scale operational challenges.

Course Description

This advanced specialization course prepares senior engineers and technical leads to deploy, operate, and continuously improve FPGA based AI inference systems at production scale. Moving beyond individual device programming, the course addresses the full operational lifecycle: multi-model serving architectures with priority scheduling; advanced power optimization including DVFS and power-domain partitioning; automated CI/CD pipelines for FPGA AI artifacts from RTL commit through hardware-in-the-loop testing; MLOps practices including telemetry collection, drift detection, and automated retraining pipelines; and fleet management with staged OTA rollouts, remote attestation, and rollback safety nets.

Course Duration: 2 Days

Course Level: Level 3

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