Course Schedule
Don’t see this course on the schedule? Submit a request and we’ll notify you when it’s available
Course
-
-
FND-07 – Altera® Hyperflex Optimization Workshop
Registration has closed or course has reached capacity.
I'm interested in this courseCourse Description This course provides a comprehensive understanding of how to create and optimize FPGA design logic to take full advantage of the Hyperflex® architecture found in all Agilex™ series […]
USD $1,800.00 -
VRF-06 – Applied Formal Verification
Registration has closed or course has reached capacity.
I'm interested in this courseCourse Description This is the foundation course of a two course formal verification progression. It delivers a complete, hands-on grounding in formal methods using SystemVerilog Assertions and the Questa Formal […]
USD $1,800.00 -
SOC-11 – RTOS Development on Altera® SoC Platforms
Registration has closed or course has reached capacity.
I'm interested in this courseCourse Description This course is built for Altera® SoC FPGA designers who want to develop deterministic, production-grade real-time systems using Zephyr RTOS on Altera SoC FPGA platforms. The course focuses […]
USD $1,800.00 -
TLS-01 – SDC Constraints & Analysis Masterclass
Registration has closed or course has reached capacity.
I'm interested in this courseCourse Description This course provides FPGA engineers with a comprehensive, hands-on mastery of Synopsys Design Constraints (SDC) authoring and static timing analysis (STA) in the Quartus® Prime Pro Edition Timing […]
USD $1,800.00 -
HDL-03 – Introduction to Verilog
Course Description This course provides a practical, hands-on foundation in using Verilog HDL for digital design. Participants will learn how to model, simulate, and verify hardware designs while developing an […]
-
TLS-02 – Quartus® Timing Closure Masterclass
This advanced course equips experienced FPGA engineers with the skills and methodology to achieve reliable, repeatable timing closure on complex Altera® FPGA designs using Quartus® Prime Pro. The course assumes […]