Target Audience: This course is designed for engineers and technical professionals who design with or evaluate Altera FPGA and SoC devices.

Course Description

This course introduces essential digital logic concepts, FPGA and SoC architecture, and practical use cases for Altera programmable devices. Starting from digital design fundamentals and progressing to advanced synchronous design practices, participants gain a thorough grounding in Altera FPGA device families, the Quartus Prime tool suite, and real-world design flows. A high-level perspective of embedded SoC design, hardware–software device partitioning, and synchronous design methodology is developed. Hands-on laboratory exercises using Quartus Prime and ModelSim reinforce every module, enabling participants to apply new skills immediately to their own projects.

Course Duration: 2 Days

Course Level: Level 1

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Target Audience: System Architects evaluating FPGA device families and performing device selection, Hardware / RTL Engineers designing logic and board-level interfaces for Altera FPGA targets, RTL / Digital Design Engineers building a structured understanding of the Quartus Prime design flow, Verification Engineers adding FPGA-based hardware prototyping to their verification methodology, FPGA Application Engineers providing technical support across the Altera device portfolio, Technical Managers and Engineering Leads requiring architectural literacy for project oversights.

Course Description

This course is offered as core material followed by two independent optional sessions.  The core material provides the essential, device-family-agnostic foundation every engineer needs before working with any Altera FPGA or SoC FPGA. It covers programmable logic history, the complete Altera device portfolio, internal FPGA fabric architecture (ALMs, memory, DSP, clocking, I/O), the Quartus Prime design flow from RTL entry through synthesis, timing closure, pin planning, and device programming, plus the high-speed connectivity features (transceivers, hard IP, DDR interfaces) common to mid-range and high-end families. The curriculum closes with simulation, on-chip debug, partial reconfiguration, and device selection methodology.

Course Duration: 3 Days

Course Level: Level 1

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Target Audience: This course is designed for experienced FPGA and SoC engineers who need deep Agilex-specific expertise, particularly those targeting data-center, AI acceleration, networking, and high-performance computing applications.

Course Description

This advanced course provides a comprehensive, ground-up treatment of the Altera Agilex FPGA and SoC device families — Agilex 5, Agilex 7, and Agilex 9 — covering every layer of the architecture from fabric tile organization through high-bandwidth memory, advanced I/O, chiplet packaging, and the CXL (Compute Express Link) subsystem that distinguishes the Agilex 9 platform in data-center and AI-acceleration markets. The course begins by exploring the architectural foundations common across the Agilex family: the Hyperflex CORE fabric with register-rich routing, the Hardened Memory Controllers and HBM2e stack integration, the Transceiver and PLL subsystems, and the Hard Processor System (HPS) in Agilex 5 and Agilex 7 SoC variants. Participants develop a detailed mental model of timing, clocking, resource utilization, and power trade-offs at the device level — knowledge that is required before attacking any advanced optimization or integration challenge.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is designed for engineers and architects who work primarily in software but need to design, evaluate, or collaborate on FPGA- and SoC-based systems. The ideal student has solid programming skills but little or no prior exposure to HDL, digital design, or programmable logic.

Course Description

This course introduces FPGA and SoC design concepts to engineers whose primary background is software development. Unlike other courses that assume prior hardware context, this course begins entirely from a C/Python mental model and systematically builds hardware thinking without requiring any prior knowledge of programmable logic or digital design.All explanations are grounded in embedded software development analogies. Topics such as parallelism, memory-mapped I/O, clock domains, and timing are presented in terms that a software engineer will immediately recognize, while progressively introducing the underlying hardware concepts. By the end of the course, students will understand RTL (VHDL/Verilog), Altera Quartus Prime for synthesis and place-and-route, working with Platform Designer (Qsys) to build SoC subsystems, and debugging designs using Signal Tap and the JTAG debug chain.

Course Duration: 2 Days 

Course Level: Level 1

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Target Audience: This course is designed for engineers who will use Quartus Prime as their primary FPGA development tool. The primary audience includes: System Architects responsible for partitioning designs between hardware and software, selecting FPGA devices, and defining system-level constraints, Hardware Engineers performing RTL design, timing closure, pin assignment, and device programming in Altera FPGA families, Software Engineers developing embedded software targeting FPGA SoC devices (Cyclone V SoC, Arria SoC) who need to understand the hardware build flow and Quartus configuration, FPGA Verification Engineers who need to set up simulation flows, interpret compilation results, and use in-system debug tools, Technical Managers and Lead Engineers evaluating Quartus Prime adoption or overseeing FPGA projects who benefit from hands-on tool experience.

Course Description

This course provides engineers with a practical introduction to the Altera® FPGA primary development environment, Quartus Prime. Participants learn to navigate the Quartus Prime interface, manage FPGA projects from creation to programming, configure target devices, apply timing and pin constraints, and understand the complete FPGA design flow within the tool.

The course emphasizes efficient project setup, best practices for tool usage, and a deep understanding of the compilation pipeline — from RTL entry through synthesis, placement and routing, timing analysis, and device configuration. Special attention is given to timing closure using the TimeQuest Timing Analyzer and to in-system debugging with the SignalTap II Logic Analyzer.

Course Duration: 2 Days 

Course Level: Level 1

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Target Audience: This course is designed for professionals who work with Altera FPGA and SoC devices and who want to automate, optimize, and scale their design workflows using Tcl scripting. Roles include: System Architects designing automated multi-device FPGA build systems and integration pipelines, Hardware / RTL Engineers automating compilation, constraint management, and timing closure, Verification Engineers scripting simulation flows, regression harnesses, and report parsing, Embedded / Software Engineers — automating SoC BSP generation, HPS configuration, and device-tree production, EDA Flow / CAD Engineers — building and maintaining corporate Tcl script libraries and EDA tool integrations.

Course Description

This course teaches system architects, hardware engineers, and software engineers how to harness the full power of the Tool Command Language (TCL) within the Altera FPGA and SoC design environment. Participants will develop practical scripting skills to automate and streamline every stage of the FPGA design flow — from project creation and constraint management through compilation, timing analysis, and SoC BSP generation.

The course opens with a thorough grounding in TCL syntax and semantics: variables, data types, strings, lists, dictionaries, conditional constructs, and loop controls. Students then move into procedural programming, file I/O, error handling, and namespace management, building a reusable library of utility procedures throughout the course.

Course Duration: 2 Days 

Course Level: Level 1

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Target Audience: This course is designed for engineers and architects who need to achieve maximum performance from Agilex™ and Stratix® 10 FPGA designs using the Hyperflex architecture.

Course Description

This course provides a comprehensive understanding of how to create and optimize FPGA design logic to take full advantage of the Hyperflex® architecture found in all Agilex™ series and Stratix® 10 FPGAs. Participants begin with a deep dive into the Hyperflex architecture and the Altera Quartus® Prime Pro Edition tool flow that targets it, then move through coding style guidelines that maximize the use of Hyper-Registers — the key building block for achieving maximum design performance. The learning plan concludes with advanced retiming and optimization strategies for the most demanding, timing-constrained designs.

Course Duration: 2 Days 

Course Level: Level 2

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Target Audience: This course is designed for engineers and architects working with Altera FPGA and SoC FPGA devices: FPGA designers who need to understand how the HPS interacts with the FPGA fabric during and after configuration, System architects designing FPGA-based embedded systems and evaluating configuration strategies, Hardware engineers responsible for FPGA board design, configuration circuitry, and power sequencing, Embedded software engineers developing bootloaders, device drivers, and RTOS/Linux BSPs for HPS-based SoC FPGAs, Firmware engineers porting U-Boot, Arm Trusted Firmware, or bare-metal code to Altera SoC FPGAs.

Course Description

This course introduces the configuration options and features available in Altera® FPGAs and SoCs. Choosing a configuration methodology is an important step in any application. This includes choosing where configuration files will be stored as well as what communication channel will be used to transfer the files. As a result, designers need to understand the supported configuration options for their target FPGA and how to implement that methodology in their system.

The course also covers the Hard Processor System (HPS) architecture for Altera® SoC FPGAs, including an overview of the Arm* Cortex family architectures. Students will learn to add and configure the processor component in a Platform Designer system from Quartus® Prime software and how to build the first-stage and second-stage bootloaders (based on U-Boot or Arm Trusted Firmware). The supported boot flows to Linux® OS and Zephyr® RTOS as well as drivers, security and single image booting will be discussed.

Course Duration: 2 Days 

Course Level: Level 1

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Target Audience: System Architects designing secure FPGA-based platforms for defense, automotive, or industrial applications, Hardware Engineers responsible for device programming, key provisioning, and anti-tamper implementation, Software Engineers developing secure boot firmware, HSM integration, or SDM-based boot flows for Agilex HPS, Security Engineers performing threat modeling, side-channel analysis, or certification work (e.g., FIPS 140-3, IEC 62443).

Course Description

This course covers AES bitstream encryption and key programming, JTAG security controls, secure boot chains for the Agilex Hard Processor System (HPS), design obfuscation techniques, Physical Unclonable Functions (PUF) integration, and side-channel attack mitigations. Altera Agilex devices expose an extensive, production-ready security infrastructure — AES-256 encryption, ECDSA-384 authentication, multi-key infrastructure, and a dedicated Secure Device Manager — that is unmatched in competing offerings. These capabilities are in high demand across defense, automotive, and industrial segments.

Course Duration: 2 Days 

Course Level: Level 3

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Target Audience: This course is designed for engineers working on complex, production-grade FPGA systems, including: Lead Engineers and Technical Managers seeking a structured framework for team-based FPGA development, System Architects who define partitioning, interfaces, and integration strategies for FPGA-based subsystems, Hardware / RTL Engineers responsible for logic design, synthesis, and timing closure, Verification Engineers developing testbenches, running simulation, and applying formal methods, Embedded Software Engineers working alongside FPGA teams on Nios or HPS-based SoC designs, FPGA Engineers transitioning from basic RTL coding to performance-optimized, production-grade designs.

Course Description

This comprehensive course consolidates the full breadth of advanced FPGA design knowledge into a single intensive program. It covers modern FPGA design methodologies used in complex, high-performance, and safety-critical systems alongside the performance optimization techniques demanded by production-grade designs. Participants move beyond coding for synthesis into disciplined FPGA system design — addressing architectural partitioning, clock and reset strategy, pipelining and retiming, DSP and memory architecture, full-spectrum verification, timing closure, high-speed I/O, power optimization, partial reconfiguration, functional safety, and team-based development workflows. Participants should expect a fast-paced, hands-on course that balances conceptual depth with practical lab work.

Course Duration: 2 Days 

Course Level: Level 1

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Target Audience: This course is designed for engineering professionals involved in FPGA and SoC product development who want to modernise their workflows using Agile methodologies and CI/CD automation. This includes: System Architects responsible for partitioning designs across FPGAs, CPUs, and SoCs, Hardware / RTL Engineers writing VHDL or Verilog targeting Altera FPGAs, Embedded Software Engineers developing bare-metal or Linux-based applications on Altera SoCs (Cyclone V SoC, Arria 10 SoC, Agilex), DevOps / Build Engineers tasked with automating FPGA compile and test flows, Engineering Managers and Technical Leads seeking to modernise FPGA team workflows, Verification Engineers integrating simulation and hardware regression into CI pipelines.

Course Description

This intensive course equips system architects, hardware engineers, and software engineers with the skills, methodologies, and tooling required to adopt Agile practices and Continuous Integration / Continuous Delivery (CI/CD) pipelines throughout the complete FPGA and SoC development lifecycle.

Participants will learn how to apply Scrum, Kanban, and SAFe frameworks to hardware-centric projects, bridging the cultural and process gap between traditional RTL development and modern DevOps practices. The course addresses the unique challenges of FPGA development — including long synthesis times, hardware-in-the-loop testing, and IP core management — and shows how modern toolchains can be orchestrated to deliver predictable, high-quality releases.

Course Duration: 2 Days 

Course Level: Level 3

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