Target Audience: This course is designed for: Software Engineers working on embedded or FPGA-adjacent software who need to understand the hardware design process, interpret hardware interfaces, or transition into RTL design roles, System Architects who specify hardware subsystems, partition designs between hardware and software, and need to read, understand, and evaluate VHDL RTL to make informed architectural decisions, Hardware Engineers and FPGA designers responsible for RTL development, design verification, synthesis, and implementation of FPGA-based systems, and Software Engineers working on embedded or FPGA-adjacent software who need to understand the hardware design process, interpret hardware interfaces, or transition into RTL design roles.

Course Description

This intensive course provides a comprehensive introduction to VHDL (VHSIC Hardware Description Language), the industry-standard language for designing, simulating, and synthesizing digital hardware. Students will progress from foundational language concepts through practical RTL design techniques, culminating in the synthesis and implementation of complete designs on Altera FPGA hardware using the Altera Quartus Prime design environment.

The course blends lecture modules with hands-on lab exercises to reinforce each topic. By the end of the course, students will be able to write synthesizable VHDL for combinational and sequential logic, build hierarchical designs, write simulation test benches, apply IP cores, and understand how VHDL maps to FPGA architecture. The course is structured to serve system architects who need design literacy, hardware engineers who will write and review RTL code, and software engineers transitioning into FPGA-based embedded development.

Course Duration: 2 Days

Course Level: Level 1

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Target Audience: This course is intended for professionals with prior VHDL and FPGA design experience, including: Software Engineers working on FPGA-accelerated systems, embedded SoC designs, or co-simulation environments, System Architects designing or evaluating complex FPGA-based subsystems and SoC architectures, and Hardware Engineers developing RTL logic, timing-critical datapaths, or high-speed interfaces on Altera FPGAs.

Course Description

This advanced, hands-on course is designed for experienced FPGA engineers who want to deepen their mastery of VHDL and apply best practices for developing high-performance, reliable, and maintainable FPGA designs. The course focuses on synthesizable VHDL, modern design techniques, and real-world development workflows used in complex FPGA and SoC projects.

Participants will explore advanced language constructs, coding patterns for timing closure and resource optimization, scalable architectures, and verification-oriented design. Each topic is reinforced through hands-on labs using realistic FPGA design tasks, that compliment the skills developed throughout the week.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is designed for engineers and architects who need to develop or review synthesizable RTL designs using Verilog HDL. It is suitable for: Software Engineers developing embedded software that interfaces closely with FPGA logic, or transitioning into hardware design roles, System Architects defining hardware/software partitions, reviewing RTL micro-architecture, and evaluating FPGA feasibility, and Hardware Engineers designing, implementing, and verifying RTL logic targeting Altera FPGAs.

Course Description

This course provides a practical, hands-on foundation in using Verilog HDL for digital design. Participants will learn how to model, simulate, and verify hardware designs while developing an understanding of synthesizable coding practices. The course combines instructor-led discussion with guided labs to reinforce key concepts and build real-world design confidence.

By the end of the course, participants will be able to write, simulate, synthesize, and implement Verilog designs targeting Altera FPGAs. Emphasis is placed on professional coding style, design reuse, and the development of verification skills that scale from simple unit tests to system-level integration.

Course Duration: 2 Days

Course Level: Level 1

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Target Audience: This course is designed for: FPGA engineers seeking to formalize and deepen their Verilog coding practices, System architects responsible for defining FPGA-based hardware architectures, Hardware engineers designing RTL logic for FPGA or ASIC targets, Software engineers transitioning to hardware development who need practical Verilog skills, and Verification engineers developing simulation environments for RTL designs.

Course Description

This course teaches designers to write professional, synthesizable RTL code using industry-standard Verilog HDL practices. Students will master the creation of hierarchical designs, state machines with controlled encoding, and parameterizable modules suitable for FPGA implementation. Practical labs reinforce every concept through hands-on work in the Altera® Quartus® Prime design software and functional simulation using Questa®-Altera® FPGA Edition. Emphasis is placed on writing clean, efficient, synthesizable code and developing effective testbench strategies for RTL-level debugging.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is intended for: Software Engineers moving into FPGA or ASIC development who require a solid grounding in synthesizable hardware description using SystemVerilog, System Architects who need to specify and partition hardware designs using modern HDL constructs and communicate design intent clearly in RTL, and Hardware Engineers (RTL Designers) who want to migrate from Verilog or VHDL to SystemVerilog, or who want to deepen their understanding of SystemVerilog’s design-centric features.

Course Description

This course is aimed at RTL designers who wish to learn about the features of SystemVerilog for RTL design. The student will learn about the constructs and features in SystemVerilog designed to capture design intent. Following best design practices enables simulation tools to analyze for correct behavior, which speeds up the design process. An introduction to SystemVerilog Assertions (SVA) is also discussed. Practical lab exercises are provided to reinforce the material.

Course Duration: 2 Days

Course Level: Level 1

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Target Audience: This course is designed for technical professionals involved in digital design and verification. It is primarily targeted towards: System architects responsible for defining verification strategies and coverage plans for complex SoC or FPGA-based designs, Hardware engineers (RTL designers) who need to write self-checking testbenches or understand the simulation environment built around their designs, Software engineers transitioning to hardware verification or embedded firmware validation roles who already have programming experience, Verification engineers looking to formalise their SystemVerilog skills and adopt structured OOP verification methodologies, FPGA engineers working on Altera-based designs who need simulation-level verification.

Course Description

This course introduces engineers to developing comprehensive verification environments using SystemVerilog. Participants will gain hands-on experience with the language features, methodologies, and best practices required to build robust, reusable verification components for complex digital designs.

The workshop begins with the extended data types, array types, enhancements to tasks and functions, and dynamic process control that distinguish SystemVerilog from traditional Verilog. It then moves into Object-Oriented Programming (OOP) modelling, showing how to design class hierarchies and assemble fully functional OOP testbenches that connect cleanly to a Design Under Test (DUT) through SystemVerilog interfaces.

Course Duration: 2 Days

Course Level: Level 1

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