Target Audience: This course is designed for technical professionals working with Altera FPGA-based embedded systems who require in-depth knowledge of the Nios V soft-core processor architecture and development ecosystem: Software Engineers developing embedded firmware, device drivers, and RTOS-based applications for Nios V processor systems, System Architects designing embedded SoC solutions on Altera FPGAs who need to evaluate and integrate the Nios V processor into product architectures, and Hardware Engineers (RTL designers) responsible for creating Platform Designer systems, adding custom peripherals, and generating HDL for FPGA implementation.

Course Description

This course provides a comprehensive introduction to the Altera Nios V soft-core processor and its ecosystem. Nios V is the next-generation RISC-V based soft-core processor for Altera FPGAs, replacing the legacy Nios II architecture. Students will gain both theoretical understanding and hands-on experience designing, configuring, and programming Nios V-based embedded systems on Altera FPGA hardware.

Beginning with the RISC-V ISA fundamentals and the Altera Platform Designer (Qsys) integration environment, the course progresses through peripheral configuration, memory subsystem design, software development using the Eclipse-based Nios V Software Build Tools (SBT), and real-time operating system integration. The final day covers advanced topics including custom instruction extensions, hardware/software co-design optimization, and system boot techniques.

Course Duration: 2 Days

Course Level: Level 1

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Target Audience: This course is designed for professionals who need to develop, support, or architect software for the HPS subsystem of Altera SoC FPGAs: Embedded Software Engineers developing bare-metal drivers, RTOS applications, or Linux device drivers targeting the HPS ARM processor, Firmware Engineers porting existing ARM Cortex-A software to Altera SoC platforms, or evaluating Zephyr RTOS as an alternative to proprietary RTOSs, Hardware Engineers who configure HPS peripherals in Platform Designer and need to understand the software interface, System Architects responsible for partitioning functionality between the HPS processor and FPGA fabric, FPGA Engineers expanding their skill set into HPS software development, Technical Leads responsible for boot architecture, memory layout, and system-level performance, and Safety Engineers evaluating or certifying embedded software stacks on Altera SoC platforms.

Course Description

This comprehensive course provides embedded software engineers, hardware engineers, firmware developers, and system architects with an end-to-end, hands-on mastery of software development for the Hard Processor System (HPS) embedded in Altera SoC FPGA devices — including the Cyclone V SoC, Arria V SoC, Arria 10 SoC, and Agilex SoC families.

The course is structured in three progressive tiers: 

• Foundation: Altera SoC architecture, boot flow, the ARM toolchain, the bare-metal development environment, linker scripts, ARM MMU & cache management, interrupt handling, and robust fault management.
• Integration & Production: HPS peripheral drivers, HPS-FPGA bridge interfacing and custom IP integration, DMA-optimised data movement, FreeRTOS multi-task development, Zephyr RTOS, U-Boot customisation, device tree authoring, and Linux kernel driver development.
• Optional — Hardware/Software Co-Design: System partitioning methodologies, FPGA fabric accelerator design using RTL and HLS, advanced AXI communication fabrics and DMA, UIO/VFIO user-space drivers, oneAPI FPGA compute, multi-core AMP partitioning with OpenAMP, functional-safety considerations, and full-stack co-design validation.

Course Duration: 3 Days

Course Level: Level 1

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Target Audience:System architects evaluating or designing FPGA-based acceleration solutions, Hardware (RTL) engineers transitioning to high-level FPGA design flows, Software engineers adding FPGA acceleration to existing applications, FPGA engineers expanding their skill set to include OpenCL-based design flows, and Embedded system developers targeting Altera SoC-FPGA platforms.

Course Description

This course provides a structured, hands-on introduction to OpenCL-based FPGA acceleration using Altera FPGAs. It is designed for system architects, hardware engineers, and software developers who are new to OpenCL on FPGAs and want to understand how high-level, data-parallel applications can be mapped efficiently onto Altera FPGA hardware. The course introduces the Altera FPGA OpenCL development model, explaining how OpenCL kernels are compiled into FPGA hardware using the Altera FPGA SDK for OpenCL (part of the Intel oneAPI toolkit). Participants learn how host-to-FPGA interactions work, how memory is organized on an FPGA-based accelerator board, and how performance differs fundamentally from CPU and GPU implementations.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: System architects designing compute-accelerated platforms who need to evaluate FPGA feasibility and throughput potential alongside CPU and GPU options, Hardware engineers with RTL/FPGA experience who want to adopt a high-level OpenCL flow to accelerate kernel development cycles, Software engineers with parallel programming background (OpenCL, CUDA, SIMD, or multi-threaded CPU) who are targeting FPGA platforms for the first time, Algorithm developers working in signal processing, computer vision, machine learning inference, or network packet processing who require deterministic, low-latency acceleration, and Embedded systems engineers integrating FPGA accelerators into SoC or PCIe-based system architectures.

Course Description

This course is built for parallel software programmers — with backgrounds in CPU/GPU computing, OpenCL, CUDA, SIMD intrinsics, or multi-threaded development — who want to target Altera FPGAs using OpenCL and achieve real, measurable acceleration rather than merely functional correctness.

The central theme is bridging the mental model gap: moving from “threads executing concurrently on cores” to “kernels becoming deeply pipelined spatial hardware with explicit data movement and bandwidth constraints.” Participants learn how Altera’s FPGA OpenCL flow compiles high-level kernel code into configurable logic, how to structure kernels for maximum pipeline throughput, and how to interpret the compiler’s feedback on initiation interval (II), loop latency, memory stall percentages, and resource utilization.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience:System Architects designing heterogeneous embedded SoC solutions that combine an ARM host processor with programmable FPGA fabric, Hardware Engineers responsible for RTL co-design, memory architecture, and IP integration within an OpenCL-based FPGA flow, Software Engineers developing host-side OpenCL runtime code, BSP integration, and real-time application software on embedded Linux or bare-metal platforms, FPGA Design Engineers transitioning from traditional RTL flows to high-level synthesis and OpenCL-based kernel development, Performance and Verification Engineers tasked with profiling, benchmarking, and validating OpenCL kernel and system throughput on SoC targets.

Course Description

This advanced course teaches system architects, hardware engineers, and software engineers how to optimize OpenCL applications specifically for embedded FPGA platforms based on Altera FPGA SoCs and embedded FPGA subsystems (e.g., ARM HPS + FPGA fabric). Unlike PCIe accelerator tuning, embedded optimization is dominated by shared memory behavior, cache effects, real-time constraints, power and thermal limits, and tight integration with platform I/O.

Participants learn how the Altera FPGA OpenCL compiler flow maps kernels into hardware pipelines and how to optimize for throughput, latency, determinism, and efficiency on embedded systems where the host typically runs on an on-chip CPU and memory is shared with the rest of the SoC subsystem. The course is report-driven and measurement-driven: students use the Altera Offline Compiler HTML report together with end-to-end profiling tools to identify bottlenecks and apply targeted kernel-level and system-level changes.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: System Architects responsible for defining FPGA platform interfaces, memory topology, and PCIe system design, Hardware Engineers implementing and verifying the RTL shell, Platform Designer systems, and hardware IP integrations, Software Engineers developing the MMD layer, PCIe Linux kernel module, host-side runtime libraries, and CI automation, FPGA Applications Engineers supporting customers who deploy OpenCL-based FPGA accelerator cards, and Platform Engineers maintaining and upgrading BSPs across Quartus Prime Pro tool releases.

Course Description

This course provides engineers with the knowledge and practical skills required to design, implement, debug, and validate a custom Altera FPGA OpenCL Board Support Package (BSP) from the ground up.

Participants begin with a targeted refresher of the OpenCL programming model and the Altera FPGA SDK for OpenCL compiler pipeline, then proceed through every layer of the BSP stack: the hardware shell (static region) built in Platform Designer, the host-side Memory Mapped Device (MMD) driver layer, the Linux PCIe kernel module, and the board_spec.xml specification file that ties all components together.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: This course is designed for technical professionals involved in Altera SoC-based product development, particularly those working at the hardware–software interface: BSP and platform engineers responsible for maintaining and extending Yocto-based Linux distributions on Altera SoC hardware, System architects designing SoC hardware–software partitioning strategies for Altera based platforms, Hardware engineers responsible for FPGA IP development who need to understand Linux driver interfaces and Device Tree binding authorship, Embedded software engineers writing Linux kernel drivers and BSP layers for Altera HPS peripherals, and Firmware engineers migrating from bare-metal or RTOS environments to Linux on Altera SoC platforms.

Course Description

Building on Linux BSP fundamentals, this course dives deep into Linux kernel driver development for HPS peripherals and custom FPGA IP on Altera SoC devices. Students write character device drivers, platform drivers, and DMA drivers, and learn to integrate custom FPGA IP blocks seamlessly into the Linux driver model. Coverage includes the Linux Device Model, DMA frameworks, and interrupt-driven driver design.

Participants gain hands-on experience configuring and extending the Device Tree to expose both HPS and FPGA-fabric peripherals to the kernel. The course covers the complete driver development workflow: from kernel module compilation and Device Tree overlay authoring, through sysfs and debugfs instrumentation, to user-space access via UIO and mmap. Each concept is reinforced with lab exercises targeting real Altera Cyclone V / Agilex SoC hardware.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: This course is designed for technical professionals who are developing or evaluating FPGA-based acceleration solutions using Altera platforms and the oneAPI toolkit. The primary audience includes: System Architects evaluating or designing heterogeneous compute platforms that include FPGA acceleration, Hardware Engineers transitioning from traditional Verilog/VHDL flows to high-level synthesis (HLS) via SYCL/DPC++, and Software Engineers responsible for host-side application code, runtime management, and FPGA kernel integration with prior OpenCL, CUDA, or SYCL experience transitioning to Intel oneAPI FPGA flows.

Course Description

This course provides engineers and architects with the knowledge and hands-on experience needed to develop high-performance FPGA acceleration solutions using Intel’s oneAPI toolkit. Students will learn to write DPC++/SYCL kernels, optimize FPGA pipelines, use the oneAPI FPGA emulator and simulator, and navigate the icpx compiler pipeline from kernel development through hardware synthesis.

This course is the designated successor to the Altera OpenCL introductory course. The OpenCL-based programming model for Altera FPGAs has been deprecated by Altera. Altera has transitioned to oneAPI and SYCL as the primary FPGA acceleration programming model. Students learning OpenCL today are learning a deprecated path for new designs — this course closes that gap with a modern, supported, and production-ready programming model.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience:This course is designed for engineers working on Altera SoC FPGA products who require deep knowledge of the Embedded Linux platform stack. Typical attendees include: DevOps / Build Engineers establishing and maintaining reproducible Yocto-based build pipelines for SoC FPGA products, System Architects defining the hardware/software partitioning strategy and selecting the SoC FPGA platform for a product, Hardware Engineers responsible for board design, FPGA fabric development, and hardware/software handoff who need to understand how their design decisions affect the Linux boot chain and driver development, and Software / Firmware Engineers developing BSPs, bootloaders, Linux kernel drivers, or application software on top of an Altera SoC FPGA platform.

Course Description

This course is the definitive program for engineers who need to master the complete Embedded Linux software stack on Altera SoC FPGA platforms. Students progress systematically from the fundamentals of the Hard Processor System (HPS) architecture, through every stage of the boot chain (BootROM, FSBL/SPL, ARM Trusted Firmware, U-Boot), across the Linux kernel and device tree layer, through Yocto-based root filesystem construction, into FPGA fabric integration and custom Linux driver development, and finally to advanced topics including boot-time optimization, runtime performance profiling, secure boot, long-term BSP maintainability, and CI/CD integration.

Course Duration: 3 Days

Course Level: Level 2

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Target Audience:Embedded software engineers responsible for the Linux software stack on Altera SoC FPGA platforms, Linux kernel driver developers transitioning into FPGA-coupled accelerator driver development, FPGA engineers who need to understand and develop the software stack that controls their hardware accelerators, System software architects designing the runtime infrastructure for edge AI SoC products, Engineers who need to deploy their custom accelerators with a production-grade software stack.

Course Description

This course covers the complete software stack for Altera SoC FPGA platforms, from Yocto BSP construction and U-Boot boot configuration through Linux device tree customization, platform driver development, DMA engine integration, and runtime inference pipeline orchestration. Starting from the HPS boot sequence and progressing through kernel-mode driver development, zero-copy DMA buffer management, and Python/ONNX Runtime integration, participants develop production-grade software infrastructure that manages custom inference accelerators. The course concludes with partial reconfiguration control from Linux, OTA update implementation.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience:This course is designed for engineering professionals working on Altera SoC FPGA platforms who require deterministic, production-grade embedded software. Typical attendees include: Verification & Integration Engineers validating real-time performance, latency budgets, and HPS↔FPGA data pipelines, System Architects defining hardware/software partitioning and real-time requirements for SoC FPGA products, Hardware Engineers responsible for FPGA IP design and HPS–FPGA interface specification who need to understand the software contract their IP must satisfy, Embedded Software Engineers developing device drivers, RTOS applications, and board bring-up for Altera HPS targets. Firmware Engineers migrating bare-metal or FreeRTOS designs to Zephyr on an Altera SoC FPGA platform.

Course Description

This course is built for Altera® SoC FPGA designers who want to develop deterministic, production-grade real-time systems using Zephyr RTOS on Altera SoC FPGA platforms. The course focuses on real-world Zephyr practices for HPS + FPGA systems: board/BSP bring-up, Zephyr device tree and driver model, interrupt and scheduling determinism, DMA and cache/coherency correctness, and robust integration of custom FPGA IP via HPS↔FPGA bridges.

Rather than teaching RTOS basics, the course concentrates on what typically blocks successful deployments: priority inversion, ISR overload, race conditions, timing jitter, non-coherent DMA corruption, device tree mismatches, and integration failures across HPS (software) and FPGA fabric (hardware). The end goal is a repeatable methodology to ship an RTOS-based SoC FPGA product with measurable real-time performance.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is designed for engineers who work on or adjacent to FPGA based embedded systems and want to incorporate MicroPython as a rapid development and scripting layer on Altera RISC-V SoC targets. The primary audience includes: FPGA Verification Engineers wanting to use MicroPython as a fast test-and-prototype scripting layer on top of HDL designs, System Architects designing embedded SoC solutions using Altera FPGA devices with RISC-V soft-processor cores, Hardware Engineers implementing and integrating RISC-V SoC subsystems in Quartus Prime / Agilex FPGA fabric, Software Engineers developing embedded firmware, drivers, and application code that run on RISC-V processors, and Embedded Systems Developers building MicroPython based applications and extending the MicroPython runtime for custom peripherals.

Course Description

MicroPython for Altera RISC-V SoC Designs is a course that teaches engineers how to deploy, customize, and develop production quality applications using MicroPython on Altera Nios V RISC-V soft-processor SoC designs. The course bridges FPGA hardware design and embedded software development, enabling students to move fluidly between Quartus Prime Platform Designer IP integration, MicroPython runtime porting, and high level Python application programming.

Starting from the RISC-V ISA fundamentals and the Altera Nios V processor family, the course guides students through building a complete SoC subsystem in Platform Designer, generating a Board Support Package (BSP), and cross-compiling the Altera ported MicroPython firmware image. Students then systematically explore the MicroPython machine module peripheral API — covering GPIO, UART, SPI, I2C, Timer, PWM, and ADC — and learn how to extend it with custom C modules that expose proprietary Avalon-MM IP to Python application code.

Course Duration: 2 Days

Course Level: Level 3

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