Target Audience: This course is designed for engineers who write, review, or validate SDC constraints for Altera FPGA designs. This includes: Software Engineers integrating FPGA IP into larger system designs and needing to validate constraints on generated subsystems, FPGA / RTL Engineers writing HDL and SDC files and driving timing closure in Quartus Prime Pro, System Architects defining clock domains, data interfaces, and board-level timing budgets, Hardware Engineers designing PCBs or FPGA subsystems that must meet strict I/O and inter-device timing requirements, and Verification Engineers performing gate-level simulation and timing sign-off on FPGA designs.

Course Description

This course provides FPGA engineers with a comprehensive, hands-on mastery of Synopsys Design Constraints (SDC) authoring and static timing analysis (STA) in the Quartus® Prime Pro Edition Timing Analyzer. The course is purpose-built around the SDC language and constraint methodology: participants will learn to write structured, maintainable, and correct SDC files that accurately model every timing relationship in an Altera® FPGA design.

Starting from the fundamentals of FPGA timing theory, the course builds systematically through clock definition (primary, generated, virtual, and PLL-derived clocks), I/O constraint methodology for source-synchronous and system-synchronous interfaces, timing exceptions (false paths, multi-cycle paths, min/max delay overrides), and advanced interface constraints covering EMIF memory interfaces and high-speed serial I/O. A dedicated module on Tcl scripting enables participants to automate constraint generation, verification, and reporting.

Course Duration: 2 Days

Course Level: Level 1

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Target Audience: This course is designed for engineers who need to close timing and resolve CDC on complex Altera FPGA designs. This includes: Software Engineers working on FPGA platforms needing to understand device-level timing behavior for co-design and integration, FPGA Design Leads and Senior RTL Engineers driving timing closure on production programs, System Architects responsible for multi-clock system partitioning, clock domain definition, and timing budget allocation, Hardware Engineers / RTL Designers writing synthesizable HDL and needing to close timing on high-frequency or multi-clock designs, and Verification Engineers validating CDC correctness through simulation and formal analysis.

Course Description

This advanced course equips experienced FPGA engineers with the skills and methodology to achieve reliable, repeatable timing closure on complex Altera® FPGA designs using Quartus® Prime Pro. The course assumes participants are already familiar with SDC syntax and focuses instead on the engineering disciplines that actually close timing: diagnosing failure root causes, restructuring logic and pipelines, applying placement and fitter controls, and managing the full clock domain crossing (CDC) design space. The course addresses the complete timing closure lifecycle: from reading failing timing reports and identifying structural bottlenecks, through architectural remedies (pipelining, retiming, register balancing), physical design controls (Logic Lock regions, placement constraints, fitter effort and seed sweeping), to scripted closure loops and production sign-off. A dedicated module on SoC and multi-IP timing challenges prepares participants for the complexity of modern Platform Designer-based subsystems.

Note: This is an advanced course. Participants are expected to have working SDC constraint authoring experience. Engineers needing to build SDC skills from the ground up should first attend the FPGA Authority “SDC Constraints and Analysis Masterclass.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is designed for engineers new to Platform Designer or transitioning from legacy Qsys/SOPC Builder flows, including: Technical leads who need to understand the Platform Designer design flow and its implications for project organization, Hardware engineers developing RTL components or working with Altera IP in FPGA/SoC designs, Software engineers targeting Nios V or HPS-based SoC platforms built with Platform Designer, System architects responsible for partitioning FPGA designs and defining inter-subsystem interfaces, FPGA engineers migrating from Qsys or moving from manual interconnect to an IP-based integration flow.

Course Description

This course provides a thorough introduction to Altera’s Platform Designer tool and guides engineers from beginner to intermediate proficiency. Starting from the fundamentals of the Platform Designer environment, students progress through the complete IP integration workflow, learn to manage clock and reset domains, develop custom IP components, and integrate processor subsystems. The course bridges traditional Qsys knowledge with current Platform Designer methodology and equips participants to tackle real-world FPGA and SoC integration projects with confidence.

Platform Designer generates the complete system hierarchy during top-level system generation, enabling a team-based hierarchical design flow where large designs can be divided into subsystems and developed simultaneously by multiple team members. This course introduces hierarchical design concepts and subsystem reuse, laying the groundwork for the advanced course that follows.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is intended for experienced Platform Designer users seeking expert-level mastery: FPGA engineers moving from competent to expert-level Platform Designer usage and tasked with establishing team design flows, System architects designing complex Avalon-based SoC and FPGA platforms who need to master performance optimization and large-scale integration, Hardware engineers integrating advanced IP cores (PCIe, Ethernet, DMA) and building reusable subsystem libraries, Verification engineers building comprehensive BFM-based simulation testbenches and automating verification workflows, and Software engineers developing JTAG-accessible firmware and working with System Console.

Course Description

This advanced course elevates engineers from solid Platform Designer users to expert-level practitioners. The first day opens with a targeted review of key intermediate concepts — BFM-based simulation, interconnect generation, and hierarchical design — reinforcing the foundation before moving into expert territory. From that point, the course focuses exclusively on the techniques and knowledge that distinguish expert-level Platform Designer engineers from competent users.

Coverage spans advanced BFM testbench construction and simulation automation, System Console-based JTAG debug and scripting, deep interconnect analysis and performance optimization, expert-level hierarchical subsystem management, high-speed serial IP integration (PCIe and Ethernet), DMA engine architecture, large SoC integration strategies, and complete design-for-reuse and IP catalog management practices.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: This course is designed for engineering professionals working with Altera SoC devices who need to develop or improve their debug capabilities: RTOS/Linux BSP engineers porting and maintaining operating systems on Altera SoC devices, Embedded software engineers developing applications and device drivers for Altera SoC platforms, Hardware engineers validating SoC hardware–software interfaces and FPGA fabric/HPS interactions, System architects designing debug and test strategies for Altera SoC-based products, and Firmware engineers responsible for bootloader bring-up and bare-metal HPS code.

Course Description

This course provides a comprehensive, structured approach to debugging software running on Altera SoC devices — including the Altera Cyclone V SoC, Arria V SoC, Arria 10 SoC, and Agilex SoC families. The course covers the full debug lifecycle from initial system bring-up through complex multi-layer application and operating-system debug.

Students learn how to build a systematic debug methodology that begins with pre-silicon planning, continues through hardware validation and U-Boot/FSBL bring-up, and extends to Linux kernel, device-driver, and user-space application debugging. Equal emphasis is placed on the tools and the thought-process: students learn not only how to operate Ashling RiscFree IDE, ARM DS, GDB, and the Quartus Signal Tap logic analyzer, but also when to apply each tool and how to interpret results efficiently.

Course Duration: 2 Days

Course Level: Level 1

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Target Audience: This course is designed for professionals who work with Altera FPGAs and SoCs and want to automate repetitive design, analysis, and verification tasks: FPGA DevOps / Build Engineers owning the automated build infrastructure for FPGA IP and SoC projects, System Architects designing multi-revision build strategies, resource-budget automation, and cross-project regression frameworks, Hardware / RTL Engineers automating compilation flows, constraint management, timing closure scripts, and bitstream generation, Software Engineers integrating FPGA build steps into CI/CD pipelines, writing HIL test harnesses, and developing internal tooling, and Verification Engineers building automated regression suites and result-diffing tools across seeds and revisions.

Course Description

This course teaches hardware engineers, software engineers, and system architects how to build robust Python-based automation scripts that drive the full Altera FPGA toolchain from the command line. Participants move beyond manual GUI-driven workflows and learn to orchestrate synthesis, place-and-route, timing analysis, IP generation, and device programming entirely through Python, using subprocess-based process control, report parsing, and structured logging.

The course balances conceptual depth with hands-on practice. Lecture modules are paired with guided lab exercises that may be performed on real Altera hardware or reference designs. Participants leave with reusable script libraries, a parameterized regression framework, and the skills to integrate FPGA build flows into modern CI/CD pipelines such as Jenkins, GitLab CI, and GitHub Actions.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is designed for engineers and architects who are ready to apply Python across the full SoC design flow: Verification Engineers building Python-driven simulation and co-simulation test environments, System Architects designing SoC-based systems integrating programmable logic and embedded processors, Hardware Engineers developing RTL/HLS-based IP cores and FPGA fabric implementations. Software Engineers writing embedded C/C++, Python-based firmware, or HLS kernels for Altera SoC devices, and FPGA Designers experienced with traditional HDL flows seeking to leverage Python-centric methodologies.

Course Description

This course is the second in the FPGA Python Developer Series. It builds directly on the Quartus automation and Python engineering skills established in the “Python CLI Scripting for Altera Tools” course, and extends them into the full breadth of Python-driven SoC hardware design.

Participants learn to describe and synthesize digital logic using Python-based hardware description libraries (PyRTL and Amaranth HDL), drive high-level synthesis compilation with Python orchestration, assemble SoC subsystems programmatically, and verify hardware IP with Python co-simulation frameworks. The course concludes with advanced topics not covered in the previous class: partial reconfiguration scripting, power analysis automation, and bitstream security.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: This course is designed for engineers and architects who design, implement, or manage FPGA-based systems requiring runtime hardware adaptability: FPGA Design Engineers seeking to adopt PR methodology to reduce power consumption, reduce device cost, or increase functional flexibility in deployed systems, System Architects designing systems that require dynamic hardware updates, adaptive computing, or multi-function FPGA platforms, Hardware Engineers responsible for partitioning designs into static and reconfigurable regions, managing PR bitstreams, and verifying PR designs, and Software Engineers who implement runtime reconfiguration management, particularly on Altera SoC platforms using HPS-hosted control flows.

Course Description

Partial Reconfiguration (PR) allows a defined region of an FPGA to be reconfigured at runtime while the remainder of the device continues to operate without interruption. This capability enables designs that can switch between multiple functional “personas”, reduce active power by powering down unused hardware, and adapt to changing protocol or algorithm requirements in deployed systems.

This course provides a rigorous, end-to-end treatment of the Altera PR design methodology using Quartus Prime Pro Edition. Topics span the complete development workflow: PR region definition and LogicLock constraints, base and persona compilation, partial bitstream generation, PR Controller IP integration, simulation and timing closure, in-system debugging with SignalTap II, and Configuration via Protocol (CvP) for PCIe-attached devices.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: This course is designed for technical professionals who need to design, optimize, or evaluate FPGA-based hardware accelerators using high-level synthesis methodologies: Algorithm developers targeting FPGA platforms for DSP, machine learning, or data-processing pipelines, System architects evaluating or adopting FPGA acceleration for compute-intensive workloads, Hardware (RTL) engineers transitioning to or augmenting their workflow with HLS-based design, Software engineers (C/C++) moving into FPGA acceleration and hardware-oriented design, and FPGA engineers seeking to shorten design iteration cycles using high-level methodologies.

Course Description

High-Level Synthesis (HLS) is a transformative methodology that enables hardware designers and software engineers to describe complex algorithms in C++ and automatically compile them into synthesizable RTL code, dramatically accelerating FPGA development cycles for compute-intensive applications.

This course provides comprehensive training in the Altera HLS Compiler Pro Edition and its integration with the Altera Quartus Prime design environment. Students learn HLS-specific C++ language extensions, optimization directives, memory architecture strategies, and the complete design flow from algorithmic specification to a programmed FPGA target.

Course Duration: 2 Days

Course Level: Level 1

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Target Audience: System Architects designing high-performance data-path and signal-processing systems on Altera FPGAs and SoCs who need to evaluate HLS as a path to near-RTL performance, Hardware Engineers experienced with RTL design who want to leverage HLS for productivity while retaining precise control over micro-architecture, Software Engineers with existing HLS experience who need to close the performance gap between compiler-generated RTL and hand-written RTL, and FPGA Design Teams looking to establish a systematic, repeatable optimization methodology for HLS-based IP development.

Course Description

This advanced course focuses on performance-critical optimization techniques for High-Level Synthesis (HLS) on Altera FPGAs using the Altera HLS Compiler Pro Edition. It is designed for engineers who have completed the “HLS for FPGA Acceleration” course (or possess equivalent hands-on HLS experience) and want to push designs from functional-but-slow to near hand-optimized RTL performance.

Rather than re-introducing HLS concepts from scratch, the course dives deeply into how the HLS compiler makes architectural decisions, how to guide those decisions explicitly, and how to optimize throughput, latency, memory bandwidth, and resource utilization on Altera FPGA fabrics. Significant emphasis is placed on understanding compiler reports, identifying and classifying performance bottlenecks, and mastering the trade-offs involved in aggressive optimization.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is designed for professionals working with or evaluating Altera SoC FPGA platforms who need to master both virtual simulation and physical HIL testing: DevOps / CI Engineers integrating simulation and physical HIL into continuous integration and delivery pipelines, System Architects designing SoC FPGA-based platforms who need to evaluate software stack behavior before hardware is available and validate it with physical hardware afterward, Hardware Engineers responsible for board and platform validation who want to accelerate development using virtual prototypes before physical units are ready, Embedded Software Engineers developing and debugging firmware, BSPs, and application software for Altera Agilex™ or Cyclone® V SoC devices, Verification and Test Engineers building automated regression environments for software running on Altera SoC FPGAs across both virtual and physical targets, Automotive / Aerospace / Industrial Control Engineers who need to integrate Altera SoC FPGA-based ECUs or control modules into domain-specific HIL rigs, and DevOps / CI Engineers integrating simulation and physical HIL into continuous integration and delivery pipelines.

Course Description

This course teaches the uses and advantages of the Simics® Simulator for Altera® SoC FPGAs through hands-on labs and structured lecture modules. Students will learn to install and configure the Simics simulation environment, create and run simulation targets for Altera SoC FPGA platforms, and use the Simics command line interface (CLI) and Python scripting engine to automate simulation workflows. The begins with hardware modelling concepts, software debugging with the Simics inspection tools, network and peripheral simulation, checkpoint and restore operations, and advanced topics including fault injection, coverage collection, and CI/CD integration. Students will be equipped to replace physical hardware with high-fidelity virtual platforms for embedded software development, regression testing, and system analysis. The half of the course introduces Hardware-in-the-Loop (HIL) testing as the complementary physical validation methodology. Students learn HIL system architecture, real-time I/O fundamentals, and hands-on integration with industry-standard HIL platforms. Domain-specific applications in automotive (ISO 26262), aerospace (DO-178C/DO-254), and industrial control (IEC 62443) are discussed, including requirements traceability, tool qualification, and hybrid virtual-plus-physical V&V strategies.

Course Duration: 3 Days

Course Level: Level 2

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Target Audience: This course is designed for professionals involved in FPGA-based system design who need to understand, estimate, measure, and reduce power consumption: System architects responsible for FPGA-based system power budgets, device selection, and thermal management of multi-chip subsystems, Hardware engineers designing RTL logic for FPGA devices who need to meet stringent dynamic and static power targets, FPGA design engineers working with Altera Cyclone, Arria, Stratix, or Agilex device families and seeking to reduce power consumption and improve energy efficiency, Software and firmware engineers developing embedded software or firmware that interacts with power-managed FPGA subsystems, including runtime DVFS and power-monitoring IP, Verification and validation engineers who need to characterize and measure FPGA power in a lab or production environment, and Design leads and technical managers overseeing low-power or thermally-constrained FPGA programs who need a thorough working knowledge of power analysis methodology.

Course Description

Power consumption is a critical design constraint in every FPGA-based system. Exceeding power budgets leads to thermal failures, shortened component lifetimes, increased cooling costs, board re-spins, and regulatory non-compliance. As FPGA designs grow in density, operating frequency, and functional integration — especially with heterogeneous SoC FPGAs such as Altera Agilex — managing power has become equally important as achieving timing closure or meeting resource targets.

This comprehensive course provides engineers and architects with the deepest available treatment of FPGA power analysis and optimization for Altera device families. The curriculum spans the complete power management lifecycle: from pre-RTL budgeting and architectural trade-off analysis, through multi-stage simulation-driven power estimation, to RTL-level and device-level optimization, board-level measurement, thermal management, system integration, and runtime power monitoring.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is intended for experienced engineering professionals working in SoC and FPGA-based product development, including: Technical Leads evaluating AI-assisted design tools for team or enterprise adoption, System Architects responsible for SoC planning, IP integration, and design partitioning, Hardware Engineers working with RTL design, synthesis, place-and-route, and timing closure, Verification Engineers developing functional verification environments and test plans, Embedded Software Engineers developing firmware, drivers, and BSPs targeting Altera SoC FPGAs, Design Methodology Engineers evaluating and deploying new EDA flows and productivity tools.

Course Description

This course equips experienced engineers and architects with the knowledge and hands-on skills needed to integrate AI agents into modern System-on-Chip (SoC) design workflows. Participants will gain a thorough understanding of large language model (LLM) capabilities and limitations, multi-agent orchestration frameworks, and retrieval-augmented generation (RAG) techniques as they apply to hardware and embedded software development.

The course begins by grounding attendees in AI agent fundamentals, then progressively builds toward advanced applications such as AI-assisted RTL generation, automated design verification, constraint management, and firmware co-development. Each day combines lecture modules with hands-on labs using industry-standard EDA tools from Altera and leading AI agent frameworks, ensuring that skills learned in class can be directly applied in production design environments.

Course Duration: 3 Days

Course Level: Level 3

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Target Audience: This course is designed for engineers and technical leads working on SoC and FPGA-based designs who want to integrate AI-agent technology into their verification workflows: Engineering Managers and Technical Leads evaluating AI-driven verification strategies for their organizations, System Architects designing SoC subsystems who need to understand AI-assisted verification capabilities and limitations, Hardware / RTL Engineers seeking to accelerate testbench development and reduce manual verification effort using AI tools, Software Engineers embedded in SoC teams who are responsible for UVM infrastructure, coverage models, or simulation automation, and Verification Engineers and Verification Leads looking to integrate AI agents into existing UVM/SystemVerilog flows.

Course Description

This course prepares system architects, hardware engineers, and software engineers to apply AI agents and large language model (LLM) technology directly within their System-on-Chip (SoC) verification flows. Participants move from first principles to production-ready pipelines, learning how AI agents can automate testbench generation, constrained-random stimulus creation, assertion writing, formal verification setup, debug triage, and coverage closure — all within an industry-standard UVM methodology.

The course blends conceptual instruction with hands-on labs. Each lab session uses a realistic SoC subsystem design (AXI4-based interconnect with peripheral IP blocks) so that every AI agent capability is demonstrated in a verification context that reflects real project conditions. By the end of the course attendees will have built, evaluated, and deployed an end-to-end AI-assisted verification pipeline.

Course Duration: 3 Days

Course Level: Level 3

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