Target Audience: This course is designed for: Any engineer who has used Quartus Prime but has not previously followed a structured debug or verification methodology, Junior and mid-level RTL engineers new to structured FPGA debug and verification methodology, Hardware engineers transitioning from board-level debug to programmable logic development, Software or embedded engineers beginning to work with FPGA or SoC designs who need grounding in RTL-layer issues, and Engineering students or recent graduates entering FPGA development roles.

Course Description

This entry-level course establishes the foundational mindset, methodology, and vocabulary that every engineer needs before approaching a debug tool. Debugging is treated not as a reactive, ad-hoc activity but as a structured, repeatable discipline that scales from single module RTL defects to full system failures on Altera FPGAs and SoC FPGA platforms.

Participants begin with the core structured debug framework: observe, hypothesize, isolate, fix, verify. They then learn to build lightweight verification plans, write self-checking simulation testbenches with bus-functional models and scoreboards, and apply SystemVerilog Assertions (SVA) as a first line of defense before any hardware is involved. The final part of the course addresses one of the most common causes of “works in simulation, fails on hardware” failures: incorrect or incomplete timing constraints. Detailed SDC constraint authoring, Quartus Timing Analyzer navigation, and CDC awareness are covered in full.

Course Duration: 2 Days

Course Level: Level 1

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Target Audience:This course is designed for: System architects who require hands-on fluency with in-system debug tool outputs for root-cause analysis, Hardware and RTL engineers responsible for FPGA design bring-up, board validation, and system-level debug, Verification engineers adding on-chip debug visibility to existing production designs, and Software engineers integrating Nios or ARM processors with custom FPGA logic peripherals who need visibility into hardware behavior.

Course Description

This hands-on course builds deep practical mastery of the complete Altera in-system debug suite available in Quartus Prime. The course brings participants to expert level proficiency through intensive laboratory work on real Altera development hardware using production quality, reference designs.

The course begins with the Signal Tap II Embedded Logic Analyzer — including advanced hierarchical trigger flow graphs, storage qualification, multi-segment capture for intermittent fault analysis, and timing-mode oversampling for setup/hold characterization, and develops Tcl scripting fluency for automating trigger configuration, data capture, and nightly regression debug workflows, complemented by power-up trigger techniques for boot fault capture and a deep exploration of Signal Probe and In-System Sources & Probes (ISSP).

Course Duration: 2 Days

Course Level: Level 1

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Target Audience:This course is designed for: System architects responsible for defining and debugging the HPS/FPGA interface specification and integration, Senior RTL and hardware engineers responsible for Altera SoC designs and full-system hardware validation, Verification engineers building advanced assertion-based and formal verification flows for SoC-scale designs, and Embedded software engineers developing HPS bare-metal drivers, Linux BSPs, and custom Linux kernel modules for FPGA fabric peripherals.

Course Description

Modern Altera SoC designs combine high-performance FPGA fabric with complex multi-clock architectures, high-speed memory and serial interfaces, embedded memories, and an Arm® based Hard Processor System (HPS) running bare metal firmware, an RTOS, or embedded Linux. When a failure appears in this environment it can originate simultaneously across RTL logic, SDC timing constraints, clock- and reset domain crossings, IP configuration, FPGA device configuration, board timing, HPS/fabric bridge connectivity, bootloader configuration, device driver code, or Linux kernel interactions. The fastest engineering teams isolate these failures rapidly by applying a systematic, layered debug methodology supported by the right combination of in-system instrumentation and software analysis tools. This advanced course equips engineers with a complete end-to-end toolkit for finding, localizing, reproducing, and fixing failures across all layers of an Altera SoC design. Coverage spans advanced SystemVerilog Assertions and nonintrusive checker binding, formal verification and structural CDC/RDC analysis using Altera Questa Formal, deep multi-clock timing closure, FPGA device configuration failure diagnosis, high speed transceivers and EMIF, HPS boot debug with the Arm Development Studio JTAG debugger, Linux BSP and kernel driver debug, RTOS task-level analysis, DMA descriptor chain diagnosis, and correlated HPS/FPGA cross-domain fault isolation using simultaneous Signal Tap and Linux ftrace.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience:This course is designed for experienced engineers who must verify the interaction between the HPS and programmable logic in Altera SoC devices: FPGA design engineers expanding into SoC co-simulation and software driven verification methodology for the first time, Verification architects responsible for defining and owning SoC level verification plans, environments, and sign-off criteria, Senior hardware/RTL engineers who must validate custom IP cores connected to HPS bridges for protocol compliance and functional correctness, Embedded software engineers writing bare metal or Linux drivers who need to validate driver and firmware behavior before physical hardware is available, and Verification engineers tasked with building, maintaining, and scaling UVM testbenches, coverage models, and regression suites for SoC designs.

Course Description

This advanced course tackles the unique and technically demanding challenges that arise when an ARM Cortex-A9/A53 Hard Processor System must be co-verified alongside custom programmable logic fabric connected through high-bandwidth AXI bridge interfaces. Participants gain hands-on experience with the complete co-simulation toolchain.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: This course is suitable for engineers and architects at all levels who are involved in the design or verification of complex digital systems: Technical Leads and Project Managers overseeing a transition to assertion-based methodologies, System Architects responsible for specifying protocol behavior and design intent, Hardware / RTL Design Engineers who want to embed self checking assertions alongside their RTL code, Verification Engineers building constrained-random and formal verification environments, and Software Engineers working on embedded firmware who need to understand hardware interfaces.

Course Description

This course is targeted towards Design and Verification engineers who wish to deploy Assertion-Based Verification (ABV) within their next project. Assertion-Based Verification is becoming a cornerstone of good design and verification practice, enabling bugs to be caught earlier, design intent to be captured precisely, and formal analysis to be applied without recoding.

SystemVerilog is one of the first hardware description languages to feature a 100% native temporal assertion syntax. The SystemVerilog Assertion (SVA) sublanguage is therefore extremely well integrated with the rest of the language, enabling assertions to be written close to the RTL, reused as Assertion IP, and deployed seamlessly in both simulation and formal verification flows.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: This course is designed for System architects, hardware (RTL) engineers, verification & software/firmware engineers, and FPGA designers.

Course Description

This is the foundation course of a two course formal verification progression. It delivers a complete, hands-on grounding in formal methods using SystemVerilog Assertions and the Questa Formal tool flow: writing properties for formal engines, modeling the environment with assumptions, running PropCheck and AutoCheck, driving the BMC and k-induction engines, debugging counterexamples, checking RTL-to-gate equivalence, and building a reusable property library.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: This course is designed for System architects, hardware (RTL) engineers, verification & software/firmware engineers working on SoC designs, and FPGA designers.

Course Description

This is the advanced course of a two course formal verification progression. It assumes comprehensive knowledge of “Applied Formal Verification” and applies formal methods to the problems that dominate real Altera SoC designs: bus protocol and interface verification, full SoC integration, clock and reset domain crossing signoff, arithmetic datapaths, security and information flow, DSP/AI accelerator blocks, large design proof scaling, and safety critical evidence — culminating in an advanced specification to signoff.

Because this course is a follow on, it does not reteach the foundation material. Instead it opens with a compact review that recaps the essentials — SVA, assume/assume-guarantee, proof engines, counterexample triage, and equivalence checking — so that students returning after the foundation course can recalibrate quickly. The review bridge adds no new depth; everything beyond it is new, advanced content.

Course Duration: 2 Days

Course Level: Level 3

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Target Audience: System architects responsible for defining verification strategies and coverage goals for Altera SoC devices, Hardware engineers (RTL designers) who must write or review UVM testbenches for IP blocks and subsystems, Software engineers developing embedded firmware that interacts with hardware peripherals and who need to understand functional verification at the register and transaction level, and Verification engineers seeking to formalize or extend their UVM skills within the Altera FPGA ecosystem.

Course Description

This course trains system architects, hardware engineers, and software engineers to design and deploy production-grade UVM testbenches aligned with the realities of Altera SoC verification. Participants learn how to translate architectural requirements into a comprehensive verification plan and implement reusable, industry-standard UVM components. The course covers all major UVM building blocks — agents, sequences, monitors, scoreboards, and functional coverage models — and applies them to the verification of common SoC building blocks: register-controlled IP, mixed memory-mapped fabrics (Avalon-MM and AXI4/AXI-Lite), streaming datapaths, DMA engines, interrupt controllers, and reset/clock-domain interactions. Hands-on lab exercises reinforce every concept.

Course Duration: 2 Days

Course Level: Level 2

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Target Audience: System architects responsible for defining verification plans and testbench architectures for complex SoC FPGA designs, Hardware / RTL engineers who write SystemVerilog RTL for Altera SoC FPGAs and wish to author advanced UVM testbenches, Software engineers integrating embedded ARM Cortex-A software stacks with FPGA fabric and requiring co-verification skills, Verification engineers and leads seeking to master advanced UVM techniques beyond basic agent/sequencer/driver patterns, and FPGA design engineers targeting Altera Agilex, Stratix 10, or Arria 10 SoC devices.

Course Description

This course provides experienced verification engineers, system architects, hardware engineers, and software engineers with a comprehensive exploration of advanced UVM techniques as applied to complex Altera SoC FPGA designs. The course provides deep coverage of formal verification methodology, Altera specific complex interface verification (HPS bridges, EMIF, PCIe Hard IP, XCVR PHY), Platform Designer subsystem verification and HPS co-simulation, simulation performance and emulation-readiness, and emerging verification techniques including the Portable Stimulus Standard and ML-driven coverage closure.

Participants move beyond foundational UVM concepts and master advanced techniques for building modular, reusable, and scalable verification environments. Emphasis is placed on real world best practices for verifying Altera SoC designs — including HPS-to-FPGA fabric interfaces, on-chip memory, high-speed serial links, and Platform Designer (Qsys) subsystems. Hands-on labs using the Altera Quartus Prime Pro toolchain reinforce every concept.

Course Duration: 2 Days

Course Level: Level 3

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