Verification and Debug Course Schedule
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Course
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VRF-02 – Altera® Debug Tools: SignalTap & System Console
Course Description This hands-on course builds deep practical mastery of the complete Altera in-system debug suite available in Quartus Prime. The course brings participants to expert level proficiency through intensive […]
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VRF-05 – SystemVerilog Assertions
Course Description This course is targeted towards Design and Verification engineers who wish to deploy Assertion-Based Verification (ABV) within their next project. Assertion-Based Verification is becoming a cornerstone of good […]
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VRF-06 – Applied Formal Verification
Course Description This is the foundation course of a two course formal verification progression. It delivers a complete, hands-on grounding in formal methods using SystemVerilog Assertions and the Questa Formal […]
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VRF-07 – Advanced Formal Verification
Course Description This is the advanced course of a two course formal verification progression. It assumes comprehensive knowledge of “Applied Formal Verification” and applies formal methods to the problems that […]
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VRF-08 – Universal Verification Methodology (UVM) Foundations
Course Description This course trains system architects, hardware engineers, and software engineers to design and deploy production-grade UVM testbenches aligned with the realities of Altera SoC verification. Participants learn how […]
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VRF-09 – Advanced UVM
Course Description This course provides experienced verification engineers, system architects, hardware engineers, and software engineers with a comprehensive exploration of advanced UVM techniques as applied to complex Altera SoC FPGA […]