FND-03 – Agilex Architecture Deep Dive

Course Description

This advanced course provides a comprehensive, ground-up treatment of the Altera Agilex FPGA and SoC device families — Agilex 5, Agilex 7, and Agilex 9 — covering every layer of the architecture from fabric tile organization through high-bandwidth memory, advanced I/O, chiplet packaging, and the CXL (Compute Express Link) subsystem that distinguishes the Agilex 9 platform in data-center and AI-acceleration markets. The course begins by exploring the architectural foundations common across the Agilex family: the Hyperflex CORE fabric with register-rich routing, the Hardened Memory Controllers and HBM2e stack integration, the Transceiver and PLL subsystems, and the Hard Processor System (HPS) in Agilex 5 and Agilex 7 SoC variants. Participants develop a detailed mental model of timing, clocking, resource utilization, and power trade-offs at the device level — knowledge that is required before attacking any advanced optimization or integration challenge.

Course Duration: 2 Days