HDL-05 – SystemVerilog for Design

Course Description

This course is aimed at RTL designers who wish to learn about the features of SystemVerilog for RTL design. The student will learn about the constructs and features in SystemVerilog designed to capture design intent. Following best design practices enables simulation tools to analyze for correct behavior, which speeds up the design process. An introduction to SystemVerilog Assertions (SVA) is also discussed. Practical lab exercises are provided to reinforce the material.

Course Duration: 2 Days