High-Level Synthesis (HLS) for FPGA Acceleration
(3 Days)

Course Description

High-Level Synthesis (HLS) enables C++ algorithmic descriptions to be automatically compiled into synthesizable RTL code, dramatically accelerating FPGA development time for compute-intensive applications. This course provides comprehensive training in the Intel HLS Compiler, covering HLS-specific C++ language extensions, optimization directives, memory architecture, and the integration of HLS-generated components into Quartus Prime designs. Use cases are also explored.

Course Duration: 3 Days