TLS-09 – High-Level Synthesis (HLS) for FPGA Acceleration

Course Description

High-Level Synthesis (HLS) is a transformative methodology that enables hardware designers and software engineers to describe complex algorithms in C++ and automatically compile them into synthesizable RTL code, dramatically accelerating FPGA development cycles for compute-intensive applications.

This course provides comprehensive training in the Altera HLS Compiler Pro Edition and its integration with the Altera Quartus Prime design environment. Students learn HLS-specific C++ language extensions, optimization directives, memory architecture strategies, and the complete design flow from algorithmic specification to a programmed FPGA target.

Course Duration: 2 Days