VRF-06 – Applied Formal Verification
Oct 19 – Oct 20
11:00 AM – 5:00 PM UTC-4 USD $1,800.00
11:00 AM – 5:00 PM UTC-4 USD $1,800.00
Course Description
This is the foundation course of a two course formal verification progression. It delivers a complete, hands-on grounding in formal methods using SystemVerilog Assertions and the Questa Formal tool flow: writing properties for formal engines, modeling the environment with assumptions, running PropCheck and AutoCheck, driving the BMC and k-induction engines, debugging counterexamples, checking RTL-to-gate equivalence, and building a reusable property library.
Course Duration: 2 Days
