VRF-09 – Advanced UVM

Course Description

This course provides experienced verification engineers, system architects, hardware engineers, and software engineers with a comprehensive exploration of advanced UVM techniques as applied to complex Altera SoC FPGA designs. The course provides deep coverage of formal verification methodology, Altera specific complex interface verification (HPS bridges, EMIF, PCIe Hard IP, XCVR PHY), Platform Designer subsystem verification and HPS co-simulation, simulation performance and emulation-readiness, and emerging verification techniques including the Portable Stimulus Standard and ML-driven coverage closure.

Participants move beyond foundational UVM concepts and master advanced techniques for building modular, reusable, and scalable verification environments. Emphasis is placed on real world best practices for verifying Altera SoC designs — including HPS-to-FPGA fabric interfaces, on-chip memory, high-speed serial links, and Platform Designer (Qsys) subsystems. Hands-on labs using the Altera Quartus Prime Pro toolchain reinforce every concept.

Course Duration: 2 Days