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  • FND-07 – Altera® Hyperflex Optimization Workshop

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    Course Description This course provides a comprehensive understanding of how to create and optimize FPGA design logic to take full advantage of the Hyperflex® architecture found in all Agilex™ series and Stratix® 10 FPGAs. Participants begin with a deep dive into the Hyperflex architecture and the Altera Quartus® Prime Pro Edition tool flow that targets […]

    USD $1,800.00

  • VRF-06 – Applied Formal Verification

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    Course Description This is the foundation course of a two course formal verification progression. It delivers a complete, hands-on grounding in formal methods using SystemVerilog Assertions and the Questa Formal tool flow: writing properties for formal engines, modeling the environment with assumptions, running PropCheck and AutoCheck, driving the BMC and k-induction engines, debugging counterexamples, checking […]

    USD $1,800.00

  • SOC-11 – RTOS Development on Altera® SoC Platforms

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    Course Description This course is built for Altera® SoC FPGA designers who want to develop deterministic, production-grade real-time systems using Zephyr RTOS on Altera SoC FPGA platforms. The course focuses on real-world Zephyr practices for HPS + FPGA systems: board/BSP bring-up, Zephyr device tree and driver model, interrupt and scheduling determinism, DMA and cache/coherency correctness, […]

    USD $1,800.00

  • TLS-01 – SDC Constraints & Analysis Masterclass

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    Course Description This course provides FPGA engineers with a comprehensive, hands-on mastery of Synopsys Design Constraints (SDC) authoring and static timing analysis (STA) in the Quartus® Prime Pro Edition Timing Analyzer. The course is purpose-built around the SDC language and constraint methodology: participants will learn to write structured, maintainable, and correct SDC files that accurately […]

    USD $1,800.00

  • HDL-03 – Introduction to Verilog

    Course Description This course provides a practical, hands-on foundation in using Verilog HDL for digital design. Participants will learn how to model, simulate, and verify hardware designs while developing an understanding of synthesizable coding practices. The course combines instructor-led discussion with guided labs to reinforce key concepts and build real-world design confidence. By the end […]

    Reserve SpotUSD $1,800.0020 spots left
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  • TLS-02 – Quartus® Timing Closure Masterclass

    This advanced course equips experienced FPGA engineers with the skills and methodology to achieve reliable, repeatable timing closure on complex Altera® FPGA designs using Quartus® Prime Pro. The course assumes participants are already familiar with SDC syntax and focuses instead on the engineering disciplines that actually close timing: diagnosing failure root causes, restructuring logic and […]

    Reserve SpotUSD $1,800.0020 spots left
    Get Course USD $1,800.00 20 tickets left