HDL and RTL Design Languages

Course Description This course is aimed at RTL designers who wish to learn about the features of SystemVerilog for RTL design. The student will learn about the constructs and features in SystemVerilog designed to capture design intent. Following best design practices enables simulation tools to analyze for correct behavior, which speeds up the design process. […]

Course Description This course introduces engineers to developing comprehensive verification environments using SystemVerilog. Participants will gain hands-on experience with the language features, methodologies, and best practices required to build robust, reusable verification components for complex digital designs. The workshop begins with the extended data types, array types, enhancements to tasks and functions, and dynamic process […]

Course Description This course provides a practical, hands-on foundation in using Verilog HDL for digital design. Participants will learn how to model, simulate, and verify hardware designs while developing an understanding of synthesizable coding practices. The course combines instructor-led discussion with guided labs to reinforce key concepts and build real-world design confidence. By the end […]

Course Description This intensive course provides a comprehensive introduction to VHDL (VHSIC Hardware Description Language), the industry-standard language for designing, simulating, and synthesizing digital hardware. Students will progress from foundational language concepts through practical RTL design techniques, culminating in the synthesis and implementation of complete designs on Altera FPGA hardware using the Altera Quartus Prime […]