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Please Select All courses of interest Please Select All courses of interest Altera® FPGA Foundations Altera® Tools and Implementation Languages AI, ML and DSP Design Altera® SoC Embedded Verification and Validation Systems

Altera® FPGA Foundations Altera® FPGA Foundations Digital Design Fundamentals for FPGA Engineers Introduction to FPGA Architecture & Altera® Devices Introduction to Altera® FPGA Architecture and Ecosystems Quartus® Prime Software Fundamentals Altera® Hyperflex Optimization Workshop Altera® SoC FPGAs: Boot and Configuration Advanced FPGA Design Methodologies FPGA Debug and Verification Techniques

Altera® Tools & Implementation Altera® Tools & Implementation Quartus® Prime Software Fundamentals Quartus® Timing Analysis & Constraints Quartus® Timing Closure Masterclass: Constraints, CDC, and STA Platform Designer (Qsys) for System Integration Altera® Quartus® Prime Software Debug Tools: Signal Tap Partial Reconfiguration with Altera® FPGAs High-Level Synthesis (HLS) for FPGA Acceleration High-Level Synthesis Advanced Optimization Techniques Simics® Simulator for Altera® FPGAs Power, Performance, and Resource Optimization Clinic Debugging & Verification Strategies

Languages Languages Introduction to Verilog Introduction to Verilog Advanced Verilog HDL Design Techniques SystemVerilog for Design SystemVerilog for Design SystemVerilog for Verification SystemVerilog Assertions Advanced VHDL for Verification Advanced FPGA Design Techniques TCL

AI, ML, and DSP Design AI, ML, and DSP Design DSP Builder for Altera® FPGAs (Model-Based Design) AI Inference on Altera® FPGAs Mastering the Altera® AI Suite DSP Primer Digital Signal Processing on FPGAs

Altera® SoC Embedded Altera® SoC Embedded Introduction to Nios® V Processors Embedded Software Development for Altera® SoCs Introduction to Platform Designer: Building Systems Advanced Platform Designer Introduction to OpenCL for Altera® FPGAs Developing a Custom OpenCL BSP OpenCL on FPGAs for Parallel Software Programmers Optimizing OpenCL Linux BSP Development for Altera® SoCs HPS Peripherals, Drivers & Device Tree Development Bare-Metal Software Development for SoC FPGAs Embedded Linux on SoC FPGA: Bootloaders, Yocto, and BSP Customization RTOS Development on Altera SoC Platforms Simics® Simulator for Altera® SoC FPGAs

Verification and Validation Verification and Validation Advanced VHDL for Verification SystemVerilog for Verification SystemVerilog Assertions Universal Verification Methodology (UVM) Altera® Quartus® Prime Software Debug Tools: Signal Tap Simics® Simulator for Altera® SoC FPGAs Advanced SoC System Design & Verification FPGA-Based Functional Safety Design FPGA Debug and Verification Techniques System-Level Verification & Hardware/Software Co-Simulation

Systems Systems I/O, Interfaces & Protocol Integration (PCIe/Ethernet/USB/Industrial) Creating PCIe Links Using FPGAs 10Gb Ethernet in Altera® FPGAs High-Speed Transceiver Design Memory Interface Masterclass FPGA Power Analysis & Optimization Functional Safety & Reliability in FPGA Designs Advanced SoC System Design & Verification Hardware/Software Co-Design Methodologies

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